Very interesting work toward a very clear vision. Incredibly competent engineers, with a management that understands what we're doing.
Very challenging work. It will almost certainly result in staying late a lot.
Aggressive market diversification appears to be working for you, so stick with it.
Interview call from career fair. 3 phone interview rounds.
Phone interview Design gates using CMOS transistors. Build gates using 2-to-1 muxes. Write a Verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency. The number of states required for a sequenc
1 Interview: * 1 question on state machines * 1 river crossing riddle * 1 question on logic design
Interview call from career fair. 3 phone interview rounds.
Phone interview Design gates using CMOS transistors. Build gates using 2-to-1 muxes. Write a Verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency. The number of states required for a sequenc
1 Interview: * 1 question on state machines * 1 river crossing riddle * 1 question on logic design