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ASIC Design Engineer Interview Experience - San Jose, California

March 1, 2013
Negative ExperienceNo Offer

Process

Direct on-site interview, no phone interview at Atheros.

Questions

Everything was easy:

  • Counter Design using Moore Machine
  • Counter Code in Verilog
  • Clock Domain Crossing Questions
  • MCP in PT

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Qualcomm ASIC Design Engineer role in San Jose, California.

Success Rate

0%
Pass Rate

Qualcomm's interview process for their ASIC Design Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive50%
Neutral0%
Negative50%

Candidates reported having mixed feelings for Qualcomm's ASIC Design Engineer interview process in San Jose, California.

Qualcomm Work Experiences