Design Verification Engineer Interview Experience - Santa Clara, California
June 1, 2012
Positive ExperienceGot Offer
Process
Phone Interview
I was called on the phone. My background was discussed.
Then, we discussed System Verilog constructs and Assertions, as well as random constraints in System Verilog.
I was then told that they would get back to me. Subsequently, I received a call from the staffing firm to inform me that I had been selected.
Questions
System Verilog Assertions
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Interview Statistics
The following metrics were computed from 1 interview experience for the Qualcomm Design Verification Engineer role in Santa Clara, California.
Success Rate
100%
Pass Rate
Qualcomm's interview process for their Design Verification Engineer roles in Santa Clara, California is incredibly easy as the vast majority of engineers get an offer after going through it.
Experience Rating
Positive100%
Neutral0%
Negative0%
Candidates reported having very good feelings for Qualcomm's Design Verification Engineer interview process in Santa Clara, California.
Qualcomm Work Experiences
4.0
Good Internship Program
Design Verification Engineer • Former Employee
Santa Clara, California, United States
November 16, 2022
Pros: Good and Flexible Work Culture
Cons: Hybrid work culture sometimes makes it difficult.
3.0
Good HW reputation, decent growth, average compensation, closed culture
Design Verification Engineer • Current Employee
Santa Clara, California, United States
September 18, 2020
Pros: - For my team, the work-life balance is good, approximately 40 hours a week plus lunch.
- The Qualcomm name easily gets you interviews in the Bay Area.
- Decent growth opportunities exist within the company.
Cons: Culture is not very open; many teams are siloed, and knowledge sharing is not common.
Compensation is average.
4.0
Design Verification Engineer contract
Design Verification Engineer • Current Employee
Santa Clara, California, United States
August 21, 2013
Pros: The methodology and workflow are professional in the industry. It's a very good opportunity for a pre-senior engineer to exercise their skills. Most engineers are working very hard. The campus location is nice, and traffic conditions are good. The on-campus gym is not bad. There are free soft drinks.
Cons: The workload is heavy. Ramp-up time is limited. Work pressure is high. The chance for staying at Qualcomm as a full-time employee is low. Project schedules are very tight. There is peer pressure.
- 4.0Good Internship ProgramDesign Verification Engineer • Former EmployeeSanta Clara, California, United StatesNovember 16, 2022Pros: Good and Flexible Work CultureCons: Hybrid work culture sometimes makes it difficult.
- 3.0Good HW reputation, decent growth, average compensation, closed cultureDesign Verification Engineer • Current EmployeeSanta Clara, California, United StatesSeptember 18, 2020Pros: - For my team, the work-life balance is good, approximately 40 hours a week plus lunch. - The Qualcomm name easily gets you interviews in the Bay Area. - Decent growth opportunities exist within the company.Cons: Culture is not very open; many teams are siloed, and knowledge sharing is not common. Compensation is average.
- 4.0Design Verification Engineer contractDesign Verification Engineer • Current EmployeeSanta Clara, California, United StatesAugust 21, 2013Pros: The methodology and workflow are professional in the industry. It's a very good opportunity for a pre-senior engineer to exercise their skills. Most engineers are working very hard. The campus location is nice, and traffic conditions are good. The on-campus gym is not bad. There are free soft drinks.Cons: The workload is heavy. Ramp-up time is limited. Work pressure is high. The chance for staying at Qualcomm as a full-time employee is low. Project schedules are very tight. There is peer pressure.
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