ASIC DFT Engineer
Description For ASIC DFT Engineer
Google is seeking an ASIC DFT Engineer to join their Devices & Services team, which combines the best of Google AI, Software, and Hardware to create innovative user experiences. This role focuses on developing custom silicon solutions that power Google's direct-to-consumer products, contributing to hardware experiences that serve millions of users worldwide.
The position requires expertise in Design for Testing (DFT) methodologies, working with various tools and technologies including Electronic Design Automation (EDA), Automatic Test Pattern Generation (ATPG), and Built-In Self Test (BIST). You'll collaborate with RTL and physical designer engineers to implement testing solutions for complex System on Chip (SoC) designs.
As an ASIC DFT Engineer, you'll be responsible for subsystem level DFT scan insertion, timing analysis, and Gate Level Simulation. The role involves working closely with executive team members to deliver critical subsystem components that ensure the quality and reliability of Google's hardware products.
This is an excellent opportunity for someone with a background in Electrical or Electronics Engineering who wants to work at the intersection of hardware design and testing. You'll be part of Google's mission to organize the world's information and make it universally accessible and useful through innovative hardware solutions.
The position offers the chance to work with cutting-edge technology in a collaborative environment, contributing to products that push the boundaries of what's possible in consumer hardware. You'll be part of a team that values diversity, equality, and inclusion, working in an environment that fosters creativity and technical innovation.
Responsibilities For ASIC DFT Engineer
- Work with a team of Design for Testing (DFT) engineers, Register-Transfer Level (RTL) and physical designer engineers
- Work on subsystem level DFT scan insertion, ATPG, no timing and timing Gate Level Simulation (GLS)
- Work with executive members of the DFT team to deliver overall deliverables for subsystems in a System on a Chip (SoC)
Requirements For ASIC DFT Engineer
- Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience
- 2 years of experience in DFT methodologies
- Experience with DFT Electronic Design Automation (EDA) tools like Tessent
- Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow
- Experience working with DFT scan insertion, ATPG and Gate level simulations
- Experience with a scripting language such as Perl or Python
- Knowledge on IJTAG, Streaming Scan Network (SSN)
