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ASIC Design Engineer Interview Experience - San Jose, California

July 1, 2016
Positive ExperienceNo Offer

Process

General questions regarding digital design. Some areas included:

  • Clock domain crossing
  • Effect of voltage and temperature on metastability of flip-flops
  • FIFO
  • Implementation of dual-port RAM using single-port RAM.

What are the different techniques to accomplish this, such as doubling the clock frequency, memory banking, or doubling the amount of data stored in the RAM?

Questions

Know the details of your past work experience.

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Interview Statistics

The following metrics were computed from 3 interview experiences for the Apple ASIC Design Engineer role in San Jose, California.

Success Rate

0%
Pass Rate

Apple's interview process for their ASIC Design Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive33%
Neutral33%
Negative33%

Candidates reported having mixed feelings for Apple's ASIC Design Engineer interview process in San Jose, California.

Apple Work Experiences