I was contacted by a hiring manager via email, and we set up an hour-long phone screen about a week later. I was asked a bunch of questions about DRC methodology, even though my expertise was in LVS. I was able to answer them fairly well, though, and was told I should get an invitation for an on-site interview. It took a couple of weeks, but I got the interview. After a mild amount of confusion between myself, the hiring manager, and the HR folks, I got the date straightened around. They paid for the entire trip, and booking it was easy and smooth.
The interview was a round-robin style with people in the department I'd be joining. I did not find it too difficult. Some of the job descriptions were about things that were not on my resume, and they asked me briefly about those to see what I knew but did not press me. They focused on discussing topics related to what was on my resume (physical verification and some scripting) or general problem-solving issues. It went pretty well, and a few of the engineers were enthusiastic about me joining the team.
I received an offer about three weeks after the interview. I did get positive feedback from the hiring manager within a couple of days, though.
Nothing really. Some pros and cons of different physical verification tools, how to filter through 100k+ errors, and how to solve chip-level LVS issues. Should be easy for experienced engineers to answer.
The following metrics were computed from 1 interview experience for the Intel Senior ASIC Design Engineer role in Hillsboro, Oregon.
Intel's interview process for their Senior ASIC Design Engineer roles in Hillsboro, Oregon is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Intel's Senior ASIC Design Engineer interview process in Hillsboro, Oregon.