Decent pay for the WLB
Decent pay for the WLB
It's a bit of a trade-off with WLB and pay. You get paid accordingly.
Upper management screwed up in the last couple of years. Hopefully, the new CEO can turn things around.
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Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
Design Verification Engineer
The interview was average. It covered basic electronic questions, including Verilog, SystemVerilog (SV), and UVM basics. The HR round was disappointing. There was no clear communication from the company regarding the next steps in the process. They
Design Verification Engineer
It was technical and behavioral. I was asked questions about my resume and all previous experience, as well as technical details of the verification components I used in those projects and other related work. I would rate them as moderate in complex
Design Verification Engineer
Haifa, IsraelJanuary 1, 2022Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
Design Verification Engineer
IndiaOctober 1, 2021The interview was average. It covered basic electronic questions, including Verilog, SystemVerilog (SV), and UVM basics. The HR round was disappointing. There was no clear communication from the company regarding the next steps in the process. They
Design Verification Engineer
San Jose, California, United StatesMay 1, 2021It was technical and behavioral. I was asked questions about my resume and all previous experience, as well as technical details of the verification components I used in those projects and other related work. I would rate them as moderate in complex
