Good Pay, Too Structured
Good Pay, Too Structured
Good pay based on workload.
Too structured and less dynamic.
Additional Ratings
Was this helpful?
Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
There were three rounds. The first interview tested our eligibility for the position, and based on that, some basic questions were asked. After a week, they confirmed that I had qualified for further rounds. They completed the two remaining interview
Design Verification Engineer
Moderate. Easy to crack if you prepare well. You need to have a good understanding of all UVM and SV concepts. Protocol concepts also help. Design knowledge is an added advantage. Please attend with proper preparation.
Design Verification Engineer
Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
Design Verification Engineer
Bengaluru, Karnataka, IndiaJanuary 1, 2021There were three rounds. The first interview tested our eligibility for the position, and based on that, some basic questions were asked. After a week, they confirmed that I had qualified for further rounds. They completed the two remaining interview
Design Verification Engineer
United StatesMarch 7, 2022Moderate. Easy to crack if you prepare well. You need to have a good understanding of all UVM and SV concepts. Protocol concepts also help. Design knowledge is an added advantage. Please attend with proper preparation.
Design Verification Engineer
Haifa, IsraelJanuary 1, 2022Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
