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ASIC Design Engineer Interview Experience

February 1, 2011
Neutral ExperienceNo Offer

Process

  1. Question related to the resume( project experience, related course)

  2. How to deal with setup time violation

  3. Does clk skew effect the hold time

4.When doing ASIC design, what should be considered regarding the power consumption

  1. Difference between ASIC design and FPGA type design

  2. Which layer of metal used for power/clock when you layout

  3. The interviewer is very patient.

Questions

Which metal layer used for power/clock

The difference between ASIC and FPGA design

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Interview Statistics

The following metrics were computed from 48 interview experiences for the Marvell Technology ASIC Design Engineer role.

Success Rate

33%
Pass Rate

Marvell Technology's interview process for their ASIC Design Engineer roles is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive35%
Neutral54%
Negative10%

Candidates reported having very good feelings for Marvell Technology's ASIC Design Engineer interview process.

Marvell Technology Work Experiences