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ASIC Design Engineer Interview Experience - Santa Clara, California

March 1, 2018
Positive ExperienceNo Offer

Process

The phone interview lasts about 45 minutes and the man is patient.

Every time I cannot figure out a problem, he tries to give me some hint to help me.

Questions

How to build a synchronizer for one bit, for multiple bits and for clock domains that run at different frequencies?

How to do truncate and the sign extension in arithmetic operation (at first I did not catch the point, and the interviewer guided me to the right answer)?

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Interview Statistics

The following metrics were computed from 16 interview experiences for the Marvell Technology ASIC Design Engineer role in Santa Clara, California.

Success Rate

31%
Pass Rate

Marvell Technology's interview process for their ASIC Design Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive44%
Neutral38%
Negative19%

Candidates reported having very good feelings for Marvell Technology's ASIC Design Engineer interview process in Santa Clara, California.

Marvell Technology Work Experiences