1.Frequency divider by 3 2.MUX finish AND,OR,XOR,XNOR function 3.Simple STA problem 4.FSM to detect 11011 5.detect how many logic 1 in circuit level 6.Bubble pushing problems 7.FIFO working function
There are 8 bits inputs,only use full adder to detect how many logic 1's
The following metrics were computed from 16 interview experiences for the Marvell Technology ASIC Design Engineer role in Santa Clara, California.
Marvell Technology's interview process for their ASIC Design Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Marvell Technology's ASIC Design Engineer interview process in Santa Clara, California.