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ASIC Design Engineer Interview Experience - Santa Clara, California

November 1, 2014
Neutral ExperienceNo Offer

Process

Apply online and after several weeks, I got phone interview. It is about ASIC design/verification. My background is more focused on verification of microprocessors, FPGA. Not very familiar with ASIC flow, so it is very important for background match.

Questions

ASIC flow, setup/hold, fix violation

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Interview Statistics

The following metrics were computed from 16 interview experiences for the Marvell Technology ASIC Design Engineer role in Santa Clara, California.

Success Rate

31%
Pass Rate

Marvell Technology's interview process for their ASIC Design Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive44%
Neutral38%
Negative19%

Candidates reported having very good feelings for Marvell Technology's ASIC Design Engineer interview process in Santa Clara, California.

Marvell Technology Work Experiences