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ASIC Design Engineer Interview Experience - Santa Clara, California

November 26, 2012
Neutral ExperienceGot Offer

Process

I was called for a phone interview first, talked about my previous experience, mainly about my resume, and was asked some simple digital circuit questions. One week after, I was scheduled for a screen interview, with 5 interviewers, that lasted more than 3 hours.

They asked some small questions, one guy still focused on the resume, some others asked some Verilog questions, some design questions, which were quite straight-forward.

Questions

All the questions are clear and normal. E.g. write FSM in Verilog, some DFT related questions.

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Interview Statistics

The following metrics were computed from 16 interview experiences for the Marvell Technology ASIC Design Engineer role in Santa Clara, California.

Success Rate

31%
Pass Rate

Marvell Technology's interview process for their ASIC Design Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive44%
Neutral38%
Negative19%

Candidates reported having very good feelings for Marvell Technology's ASIC Design Engineer interview process in Santa Clara, California.

Marvell Technology Work Experiences