The first round was a phone interview of around 45 minutes. It was focused entirely on linear pipeline and Out of Order Pipeline principles.

The second round was a face to face interview at Santa Clara. There were 4.5hrs of interview (45 minutes per interviewer), which was completely technical focussing on FSM, Verilog design, Cache and Tomasulo Out of order implementation.

1st Round : Talked about RAW,WAW and WAR hazards and how is it solved/handled in both linear and OoO pipelines. Structural hazards caused and handled in OoO pipelines.

2nd Round: Was interviewed by 5 interviewers (45 minutes with each). Focussed entirely on my resume. Asked in depth questions on Tomasulo out of Order Implementation and Multi Clock Domain Fifo Design. Some of the questions were on Sequence Detectors, Simple Verilog design questions, Frequency Dividers and circuitry design.

One of the interviewers gave a scenario and asked to write a code to validate the integrity of the circuit (to test our VERIFICATION thinking ).