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ASIC Design Engineer Interview Experience - United States

January 21, 2015
Positive ExperienceGot Offer

Process

Phone interview for very basic digital design question i.e. setup/hold time, max clock frequency, and some project questions. Received onsite interview after 2 weeks, asked very detailed on my Verilog project, FSM, FIFO, cross domain clock, little Perl and OOP.

Questions

Never learned Perl before so did not answer.

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Interview Statistics

The following metrics were computed from 36 interview experiences for the Marvell Technology ASIC Design Engineer role in United States.

Success Rate

33%
Pass Rate

Marvell Technology's interview process for their ASIC Design Engineer roles in the United States is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive39%
Neutral50%
Negative11%

Candidates reported having very good feelings for Marvell Technology's ASIC Design Engineer interview process in United States.

Marvell Technology Work Experiences