Phone interview for very basic digital design question i.e. setup/hold time, max clock frequency, and some project questions. Received onsite interview after 2 weeks, asked very detailed on my Verilog project, FSM, FIFO, cross domain clock, little Perl and OOP.
Never learned Perl before so did not answer.
The following metrics were computed from 36 interview experiences for the Marvell Technology ASIC Design Engineer role in United States.
Marvell Technology's interview process for their ASIC Design Engineer roles in the United States is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Marvell Technology's ASIC Design Engineer interview process in United States.