First round with hiring manager. No introduction. He went right into technical questions. Asked me 3 technical questions. He looked rushed and tired.
Next I went for onsite.
6 rounds. 1 staff member. Asked me standard system Verilog questions. Nice to interact with.
Rest 5 were all senior principal engineers. Most looked very tired and rushed. One was mad and disappointed as I could not answer one of his questions. It felt like they are contractors for other companies. HR should train them regarding how to behave in an interviews.
Questions - lots of UVM, system Verilog questions
What are the UVM phases, and why are they used?
The following metrics were computed from 1 interview experience for the Marvell Technology Staff Design Verification Engineer role in United States.
Marvell Technology's interview process for their Staff Design Verification Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having very negative feelings for Marvell Technology's Staff Design Verification Engineer interview process in United States.