Great learning experience with cutting-edge technology
Great learning experience with cutting-edge technology
Marvell provides hands-on experience with industry-leading technology, offering valuable exposure to real-world ASIC development. The team is highly skilled and supportive, and there’s a collaborative work environment. The internship program also offers meaningful projects that help interns grow professionally. There is an excellent work-life balance.
While the internship was rewarding, the onboarding process could have been more streamlined.
Additionally, as an intern, there were limited opportunities for cross-team interaction, which would have been helpful for broader networking.
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Marvell Technology Interview Experiences
ASIC Design Engineer
Apply online and after several weeks, I got phone interview. It is about ASIC design/verification. My background is more focused on verification of microprocessors, FPGA. Not very familiar with ASIC flow, so it is very important for background match.
Senior ASIC Design Engineer
The interview process is standard, first, there is a telephonic screen which is totally technical, and lasts about an hour. Then they call you for an onsite interview, which lasts about 5 hours, with 5 one-on-one interviews with the whole team. The
ASIC Design Engineer
1.Frequency divider by 3 2.MUX finish AND,OR,XOR,XNOR function 3.Simple STA problem 4.FSM to detect 11011 5.detect how many logic 1 in circuit level 6.Bubble pushing problems 7.FIFO working function
ASIC Design Engineer
Santa Clara, CaliforniaNovember 1, 2014Apply online and after several weeks, I got phone interview. It is about ASIC design/verification. My background is more focused on verification of microprocessors, FPGA. Not very familiar with ASIC flow, so it is very important for background match.
Senior ASIC Design Engineer
Santa Clara, CaliforniaMarch 1, 2013The interview process is standard, first, there is a telephonic screen which is totally technical, and lasts about an hour. Then they call you for an onsite interview, which lasts about 5 hours, with 5 one-on-one interviews with the whole team. The
ASIC Design Engineer
Santa Clara, CaliforniaJuly 1, 20121.Frequency divider by 3 2.MUX finish AND,OR,XOR,XNOR function 3.Simple STA problem 4.FSM to detect 11011 5.detect how many logic 1 in circuit level 6.Bubble pushing problems 7.FIFO working function
