Great learning experience
Great learning experience
Smaller teams make a great place to learn.
Management needs major improvement and
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Marvell Technology Interview Experiences
ASIC Verification Engineer
Contacted by hiring manager and got arranged a phone interview a week later. First self-introduce. Then got asked four technical questions. Clock frequency divider, digital circuit design- given 4 inputs, outputs and timing diagram to design gate lev
ASIC Verification Engineer
Phone screen followed by in person interview. The interview was easy but I was not a match
ASIC Verification Engineer
Applied online. Got call after 1 month. Asked question on resume and question related to basic design, OOPs and System Verilog. The interviewer was friendly and gave some hints to solve the problems. The interview went for almost 1 hour 15 minutes.
ASIC Verification Engineer
Santa Clara, CaliforniaOctober 1, 2012Contacted by hiring manager and got arranged a phone interview a week later. First self-introduce. Then got asked four technical questions. Clock frequency divider, digital circuit design- given 4 inputs, outputs and timing diagram to design gate lev
ASIC Verification Engineer
San Jose, CaliforniaJuly 1, 2010Phone screen followed by in person interview. The interview was easy but I was not a match
ASIC Verification Engineer
San Jose, CaliforniaApril 1, 2019Applied online. Got call after 1 month. Asked question on resume and question related to basic design, OOPs and System Verilog. The interviewer was friendly and gave some hints to solve the problems. The interview went for almost 1 hour 15 minutes.
