Contacted by hiring manager and got arranged a phone interview a week later. First self-introduce. Then got asked four technical questions. Clock frequency divider, digital circuit design- given 4 inputs, outputs and timing diagram to design gate level circuits, Verilog question about signed and unsigned integer... The interviewer was very nice and asked me about my interest.
I am checking the black box CRC circuit.
The following metrics were computed from 2 interview experiences for the Marvell Technology ASIC Verification Engineer role in Santa Clara, California.
Marvell Technology's interview process for their ASIC Verification Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Marvell Technology's ASIC Verification Engineer interview process in Santa Clara, California.