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Design Verification Engineer Interview Experience - Sunnyvale, California

February 1, 2024
Neutral ExperienceNo Offer

Process

One round phone interview.

Five rounds of virtual onsite interviews.

Four out of six interviews are technical, asking about UVM, SystemVerilog, and test plans. The other two are behavioral and leadership questions. There are a lot of coding questions.

Questions

Write a test plan for a 2x2 switch arbiter.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Meta Design Verification Engineer role in Sunnyvale, California.

Success Rate

0%
Pass Rate

Meta's interview process for their Design Verification Engineer roles in Sunnyvale, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for Meta's Design Verification Engineer interview process in Sunnyvale, California.

Meta Work Experiences