Work-life balance and good pay.
No cons as of now.
Very detailed interview, with specific technical questions for the role. Prepared and attentive managers. Interview duration: one hour. There were several interviews, some of which were in English, via video conference.
Basic questions on SystemVerilog and Verilog, and basic OOP concepts. UVM concepts like config and factory. Some test bench related questions. First round was an initial phone screening interview. The second was also the same, but more technical.
Telephonic and phase-to-phase with a group panel, two rounds in phase-to-phase. IQ test, technical questions. In phase-to-phase, they asked questions about previous problems and problem-solving approaches.
Very detailed interview, with specific technical questions for the role. Prepared and attentive managers. Interview duration: one hour. There were several interviews, some of which were in English, via video conference.
Basic questions on SystemVerilog and Verilog, and basic OOP concepts. UVM concepts like config and factory. Some test bench related questions. First round was an initial phone screening interview. The second was also the same, but more technical.
Telephonic and phase-to-phase with a group panel, two rounds in phase-to-phase. IQ test, technical questions. In phase-to-phase, they asked questions about previous problems and problem-solving approaches.