Great work culture with interesting work given.
The learning curve when starting this job is very high if you don't really have experience in this field.
Basic questions on SystemVerilog and Verilog, and basic OOP concepts. UVM concepts like config and factory. Some test bench related questions. First round was an initial phone screening interview. The second was also the same, but more technical.
Very detailed interview, with specific technical questions for the role. Prepared and attentive managers. Interview duration: one hour. There were several interviews, some of which were in English, via video conference.
First round was an online test of 1 hour consisting of: * Basic electronics, mostly digital design and CMOS-related. * Aptitude questions of medium difficulty. Second round was a technical round where they asked more about digital design and ti
Basic questions on SystemVerilog and Verilog, and basic OOP concepts. UVM concepts like config and factory. Some test bench related questions. First round was an initial phone screening interview. The second was also the same, but more technical.
Very detailed interview, with specific technical questions for the role. Prepared and attentive managers. Interview duration: one hour. There were several interviews, some of which were in English, via video conference.
First round was an online test of 1 hour consisting of: * Basic electronics, mostly digital design and CMOS-related. * Aptitude questions of medium difficulty. Second round was a technical round where they asked more about digital design and ti