Building products on the frontier of the consumer electronics and software industry.
The company treats its employees well, and I feel respected.
The company has a lot of resources and is willing to invest heavily to be successful in the market.
Satya Nadella has been changing the company culture for the better, inspiring more innovative thinking and collaboration across teams at all levels.
The large corporate structure could be a negative for some. High-level decisions are often made out of view of individual contributors, which can be frustrating without a lack of context.
Continue being aggressive with investments in mobile and new hardware products that push the envelope.
Inspire innovation from all levels and improve processes to bubble up product ideas from lower levels.
I received a call from HR stating that my resume was shortlisted and I received an invitation. There were two rounds scheduled. The first round went really well. In the second round, I joined the call, but the interviewer didn't show up. I requeste
Very easy interviews. Only experience-based questions were asked. There were 4 rounds, all from the US. Brush up on protocol overviews, data center systems, and debug and diagnostic flows.
I had phone screens with them twice, for two different teams. The interviewers were polite and friendly. I wouldn't say there were tough questions. One of them included a one-hour Verilog coding exercise. I was asked about clock-domain crossing and
I received a call from HR stating that my resume was shortlisted and I received an invitation. There were two rounds scheduled. The first round went really well. In the second round, I joined the call, but the interviewer didn't show up. I requeste
Very easy interviews. Only experience-based questions were asked. There were 4 rounds, all from the US. Brush up on protocol overviews, data center systems, and debug and diagnostic flows.
I had phone screens with them twice, for two different teams. The interviewers were polite and friendly. I wouldn't say there were tough questions. One of them included a one-hour Verilog coding exercise. I was asked about clock-domain crossing and