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ASIC Design Engineer Interview Experience - Toronto, Canada

February 1, 2019
Neutral ExperienceNo Offer

Process

I applied through the university career fair. There, they asked me to explain one of the projects I had done and how I would rate my Verilog skills.

After three weeks, they emailed me to set up a phone interview. During the phone interview, they explained the roles they were looking for and asked about my background. This was followed by a series of technical questions about clock domain crossing, setup and hold time, and clock skew.

Questions

In ASIC design, is hold time more critical than setup time?

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Qualcomm ASIC Design Engineer role in Toronto, Ontario.

Success Rate

50%
Pass Rate

Qualcomm's interview process for their ASIC Design Engineer roles in Toronto, Ontario is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive50%
Neutral50%
Negative0%

Candidates reported having very good feelings for Qualcomm's ASIC Design Engineer interview process in Toronto, Ontario.

Qualcomm Work Experiences