Process
Two rounds of telephone interview.
First round, asked about projects related to Xilinx FPGA, setup time, hold time, and assertion and deassertion of an asynchronous reset signal. Verilog code for a flip-flop. C code for sorting. Took 30 minutes.
Second round was a manager interview. Asked about projects related to Xilinx FPGA. Asked how I did P&R. I said we didn't do anything, Xilinx automatically generates the mapping. He was disappointed. Then he asked about my experience with PrimeTime. I don't have much. He was disappointed. Asked if I know regular expressions. I don't know. He was disappointed. Took only 20 minutes. Done.
Questions
Assertion and deassertion of asynchronous reset signal: What's the effect on the system?
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Interview Statistics
The following metrics were computed from 1 interview experience for the Sandisk ASIC Design Engineer Intern role in United States.
Success Rate
Sandisk's interview process for their ASIC Design Engineer Intern roles in the United States is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having very negative feelings for Sandisk's ASIC Design Engineer Intern interview process in United States.
Sandisk Work Experiences
- 4.0dddTest Engineer • Current EmployeeBengaluruNovember 18, 2021Pros: Good company; decent growth; good stock.Cons: Poor management; Too much of meetings
- 4.0Senior Device EngineerSenior Device Engineer • Current EmployeeMilpitas, CAJuly 12, 2016Pros: Nice environment and friendly coworkers.Cons: Low challenging work and no creative job.
- 3.0Unprofessional managerStaff Firmware Engineer • Former EmployeeBengaluruFebruary 28, 2019Pros: Benefits and salaries depend on the team. Timing flexibility and new technologies to learn.Cons: Bad management, too much politics, favoritism, and no appreciation. Bossism in some teams. Some leads should learn the definition of it.
