Interacted with a hiring manager at a college career fair and got called on-site for the next week.

The campus interview/conversation was more discussion-based, as opposed to being asked questions. They were looking more to gauge past work experience, I think.

For the on-site interview, I met with almost everyone on the team. The questions ranged from basic scripting to understanding of various aspects of the ASIC Design flow, and even some Verilog and digital logic.

There was nothing that was below the gate/logic level; I was not given transistor-level circuits.

It was a whole-day process, starting in the morning and ending in the evening.

Synthesis concepts - flow, different types of libraries, process corners, some PD basics, etc.

Async FIFO in Verilog, with relatively detailed conceptual questions.