He asked me what a virtual function is and what the difference is between a task and a function in Verilog. Also, the basic stuff about setup time and hold time.
In the end, he asked me how to communicate data through different time domains.
How to communicate data through different time domains.
The following metrics were computed from 1 interview experience for the Sandisk Verification Engineering role.
Sandisk's interview process for their Verification Engineering roles is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Sandisk's Verification Engineering interview process.