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Verification Engineering Interview Experience

October 1, 2012
Positive ExperienceNo Offer

Process

He asked me what a virtual function is and what the difference is between a task and a function in Verilog. Also, the basic stuff about setup time and hold time.

In the end, he asked me how to communicate data through different time domains.

Questions

How to communicate data through different time domains.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Sandisk Verification Engineering role.

Success Rate

0%
Pass Rate

Sandisk's interview process for their Verification Engineering roles is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Sandisk's Verification Engineering interview process.

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