Design Verification Engineer, HW Compute Group
Description For Design Verification Engineer, HW Compute Group
Amazon Lab126's Hardware Compute Group is seeking a Senior Design Verification Engineer to join the team that built the innovative Silicon IP AZ1 Neural Edge powering the latest generation of Echo devices. This role focuses on defining verification methodology and implementing test plans for sub-systems and full chip development.
The position involves working with multi-disciplinary teams including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering to architect and implement complex functional blocks for world-class hardware devices. Key responsibilities include designing verification environments using SystemVerilog and UVM, writing C-based tests, debugging with design engineers, and ensuring comprehensive coverage for successful tape-out.
The ideal candidate will work on verifying complex IP blocks that will be integrated into SOCs and silicon for consumer devices. You'll be responsible for:
- Designing world-class hardware and software verification solutions
- Creating and enhancing constrained-random verification environments
- Writing comprehensive test plans and coverage measures
- Debugging tests with design engineers
- Working across multiple verification platforms including UVM testbench, FPGA, and emulator
This is an opportunity to join the team that's continuing to innovate in ML accelerator technology at the edge, working with cutting-edge technology in a collaborative environment. The role offers competitive compensation ranging from $129,800 to $212,800 per year based on location, plus comprehensive benefits including medical, financial, and other benefits.
The position requires strong technical skills in semiconductor design verification, excellent communication abilities, and the capability to work independently while collaborating effectively with cross-functional teams.
Responsibilities For Design Verification Engineer, HW Compute Group
- Design Verification of Subsystems such as CPU, NPU, and SOC
- Drive Verification Methodology using System Verilog / C++ based test benches
- Define verification methodology and implement test plans
- Create and enhance constrained-random verification environments
- Debug tests with design engineers
- Close coverage measures and identify verification holes
- Participate in test plan and coverage reviews
Requirements For Design Verification Engineer, HW Compute Group
- Bachelor's degree or equivalent in EE, CE, or CS
- 3+ years of practical semiconductor design verification experience
- Experience with System Verilog, UVM, assertions and coverage driven verification
- Experience using multiple verification platforms: UVM test bench, FPGA, emulator
- Experience defining verification methodologies
- Experience with test plan development and verification infrastructure
- Strong debug skills for architecture, algorithms, functionality and performance
- Experience with industry standard tools and scripting languages (Python or Perl)
Benefits For Design Verification Engineer, HW Compute Group
- Medical benefits
- Financial benefits
- Comprehensive benefits package
