CAD Engineer - Timing for Gate-Level Flows & Methodologies
Description For CAD Engineer - Timing for Gate-Level Flows & Methodologies
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.
As a CAD Engineer focusing on Timing for Gate-Level Flows & Methodologies, you will be an integral part of the STA CAD team working to improve the performance of Apple Silicon. Your role involves managing all aspects of static timing methodologies and addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams.
Key Responsibilities:
- Develop and enhance gate-level STA flows for Apple silicon designs
- Debug issues related to constraints, flow scripts, and timing closure
- Drive STA methodology improvements for efficiency and silicon timing correlation
- Create and maintain timing analysis and power reduction scripts
- Support verification methodologies and best practices across design teams
- Conduct timing path analysis and post-silicon timing debug
- Collaborate with EDA vendors on technical solutions
Requirements:
- BS degree with 10+ years of relevant industry experience
- Expert-level knowledge of static timing analysis tools and flows
- Strong programming skills in Python and Tcl
- Experience with large high-performance SoC designs
- Deep understanding of timing constraints and validation
- Excellent communication and problem-solving abilities
Benefits:
- Competitive base pay range: $181,100 - $318,400
- Comprehensive medical, dental, and vision coverage
- Retirement benefits and stock programs
- Education reimbursement
- Potential for bonuses and relocation assistance
Join Apple's Silicon Technologies group and be part of the team that creates the technology powering millions of beloved Apple devices worldwide.
Responsibilities For CAD Engineer - Timing for Gate-Level Flows & Methodologies
- Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs
- Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure
- Facilitate and drive STA methodology changes to improve overall STA flows
- Develop and maintain scripts and methods for timing analysis and power reduction
- Develop and support methodologies, tools, and flows used in verification
- Analysis of timing paths to identify key issues, including post-silicon timing debug
- Work closely with EDA vendors to develop and incorporate new capabilities
Requirements For CAD Engineer - Timing for Gate-Level Flows & Methodologies
- BS and 10+ years of relevant industry experience
- Expert power user of static timing analysis tools and flows
- Advanced programming skills with Python and Tcl or other high level programming languages
- Familiar with STA of large high-performance SoC designs in deep sub-micron technologies
- Deep understanding of noise, cross-talk, variation, margins, and timing models
- Knowledge of timing/SDC constraints
- Excellent communication skills
Benefits For CAD Engineer - Timing for Gate-Level Flows & Methodologies
- Medical Insurance
- Dental Insurance
- Vision Insurance
- 401k
- Equity
- Education Budget
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