CAD Engineer - Timing for Gate-Level Flows & Methodologies

Do you love creating elegant solutions to highly complex challenges? As part of Apple's Silicon Technologies group, you'll help design and manufacture next-generation, high-performance, power-efficient processors and system-on-chip (SoC). As a CAD Engineer focusing on Timing for Gate-Level Flows & Methodologies, you'll be an integral part of improving Apple Silicon performance. You'll be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through development of flows and methodologies used by all Apple Silicon teams.

Your role involves developing and maintaining gate-level STA flows, working closely with design teams to debug timing issues, and driving methodology improvements. You'll create scripts for timing analysis, verify timing constraints, and work on post-silicon timing debug. This position requires expertise in static timing analysis tools, advanced programming skills, and deep understanding of timing models and constraints.

You'll be joining a team that enables Apple's devices to seamlessly handle tasks beloved by millions. Your work will directly impact the performance and efficiency of Apple's custom silicon, which powers their innovative product lineup. This is an opportunity to work with cutting-edge technology while collaborating with world-class engineers and EDA vendors to solve complex technical challenges.

The ideal candidate combines technical expertise with excellent communication skills, can work effectively with various teams, and has a proven track record in CAD flow development. You'll be part of Apple's journey in pushing the boundaries of silicon technology, making this an exciting opportunity for someone passionate about hardware engineering and timing analysis.