CAD Engineer - Timing for Gate-Level Flows & Methodologies
Description For CAD Engineer - Timing for Gate-Level Flows & Methodologies
Do you love creating elegant solutions to highly complex challenges? As part of Apple's Silicon Technologies group, you'll help design and manufacture next-generation, high-performance, power-efficient processors and system-on-chip (SoC). You'll be responsible for crafting and building the technology that fuels Apple's devices, ensuring they can seamlessly handle tasks beloved by millions.
As a CAD Engineer on the STA CAD team, you will be integral to improving Apple Silicon performance. Your role focuses on static timing methodologies, addressing timing challenges on advanced tech nodes through flow and methodology development. You'll work with all Apple Silicon teams to drive timing analysis and closure for first-time-right silicon.
Key responsibilities include developing gate-level STA flows, debugging timing issues, enhancing methodologies for improved efficiency, and working closely with design teams and EDA vendors. You'll leverage your expertise in static timing analysis, programming (Python/Tcl), and deep understanding of timing constraints to drive innovation in our silicon design process.
This role offers the opportunity to impact Apple's cutting-edge silicon development, working with advanced technologies and contributing to products used by millions worldwide. You'll collaborate with talented engineers while solving complex technical challenges in a dynamic, innovation-driven environment.
Responsibilities For CAD Engineer - Timing for Gate-Level Flows & Methodologies
- Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs
- Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure
- Facilitate and drive STA methodology changes to improve overall STA flows
- Develop and maintain scripts and methods for timing analysis and power reduction
- Develop and support methodologies, tools, and flows for timing constraints verification
- Analysis of timing paths to identify key issues, including post-silicon timing debug
- Work closely with EDA vendors to develop and incorporate new capabilities
Requirements For CAD Engineer - Timing for Gate-Level Flows & Methodologies
- BS and 10+ years of relevant industry experience
- Expert power user of static timing analysis tools and flows
- Advanced programming skills with Python and Tcl
- Proven track record of development and deployment of complex CAD flows
- Familiar with STA of large high-performance SoC designs
- Deep understanding of noise, cross-talk, variation, margins, and timing models
- Knowledge of timing/SDC constraints
- Excellent communication skills
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