CAD Engineer - Timing for Gate-Level Flows & Methodologies

Join Apple's Silicon Technologies group as a CAD Engineer specializing in timing for gate-level flows and methodologies. In this role, you'll be part of the team that designs and manufactures next-generation, high-performance, power-efficient processors and system-on-chip (SoC) solutions. As a member of the STA CAD team, you'll play a crucial role in improving Apple Silicon performance through developing and maintaining static timing methodologies and flows.

You'll work on complex challenges related to timing analysis and closure, ensuring first-time-right silicon across all Apple Silicon teams. Your responsibilities will span from developing and enhancing gate-level STA flows to collaborating with design teams on debugging timing issues. You'll also drive methodology improvements to enhance efficiency and productivity while maintaining silicon timing correlation.

The role combines technical expertise in static timing analysis with collaborative problem-solving, as you'll work closely with both internal teams and EDA vendors. You'll be responsible for developing scripts for timing analysis, power reduction, and constraint verification, while also participating in post-silicon timing debug efforts.

This position offers the opportunity to directly impact Apple's renowned silicon designs, working with cutting-edge technology and advanced tech nodes. You'll be part of a team that enables millions of customers to seamlessly use Apple devices, contributing to the company's reputation for excellence in hardware design and performance.

Benefits include a competitive base salary range of $147,400 to $272,100, comprehensive medical and dental coverage, retirement benefits, stock programs, education reimbursement, and potential bonuses. Join Apple's innovative hardware team and help shape the future of silicon technology while enjoying excellent compensation and benefits.