CAD Engineer - Timing for Gate-Level Flows & Methodologies

Apple's Silicon Technologies group is seeking a CAD Engineer to join their STA CAD team, focusing on improving the performance of Apple Silicon. This role is integral to the development and enhancement of static timing methodologies and flows used across Apple Silicon teams.

The position involves working with advanced technology nodes to address timing challenges and ensure first-time-right silicon through comprehensive timing analysis and closure methodologies. You'll be part of the team responsible for crafting and building the technology that powers Apple's devices, directly impacting millions of users worldwide.

As a CAD Engineer, you'll be responsible for developing and maintaining gate-level STA flows, collaborating with design teams on timing closure, and implementing methodology improvements for enhanced efficiency. The role requires expertise in static timing analysis, programming skills (particularly Python and Tcl), and a deep understanding of SoC design timing constraints.

The ideal candidate will have at least 3 years of industry experience, strong programming fundamentals, and expertise in static timing analysis tools and flows. Knowledge of noise, cross-talk, variation, and timing margins is essential, as is the ability to communicate effectively with management and follow solutions through to completion.

Apple offers a comprehensive benefits package including competitive base pay ($143,100 - $264,200), stock options, medical/dental coverage, retirement benefits, education reimbursement, and various other perks. The role is based in Sunnyvale, California, and offers the opportunity to work on cutting-edge technology that impacts millions of Apple users worldwide.

Join Apple's Silicon Technologies group to be part of a team that's pushing the boundaries of processor and SoC design, ensuring Apple products maintain their reputation for exceptional performance and efficiency.