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Physical Design PPA Engineer

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Description For Physical Design PPA Engineer

We are looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality. You will be responsible for generating automation and infrastructure to scale and improve the efficiency and reliability of the PPA regression and problems. You'll collaborate with CAD and design teams to drive improvements and updates in production design flows. You'll work cross-functionally with design, power, post-silicon, and CAD teams to deliver on PPA goals.

Key responsibilities include:

  • Deep dive to root cause and address unexpected results
  • Collaborate on SOC design efforts
  • Generate automation and infrastructure for PPA regression
  • Work with various teams to improve production design flows
  • Integrate and develop new insights

We're seeking a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems. You'll be part of an exciting silicon design group responsible for designing state-of-the-art ASICs. This role offers the opportunity to work on groundbreaking projects and help design tools that bring customers experiences they've never before envisioned.

Join us in crafting entirely new solutions and turning forward-thinking ideas into reality!

Last updated 8 months ago

Responsibilities For Physical Design PPA Engineer

  • Generate automation and infrastructure for PPA regression
  • Analyze and address unexpected results in PPA
  • Collaborate with CAD and design teams to improve production design flows
  • Work cross-functionally to deliver on PPA goals
  • Participate in SOC design efforts
  • Evaluate new Stdcell libraries in leading tech nodes
  • Analyze physical databases and drive new ideas
  • Contribute to ASIC integration flows
  • Assist in tapeout processes and verification flows
  • Implement ECOs for functional and timing closure

Requirements For Physical Design PPA Engineer

  • BS and a minimum of 3 years of relevant industry experience
  • Strong understanding of RTL2GDSII flow and concepts
  • Hands-on experience in PPA analysis for different Physical designs
  • Familiarity with development of block/partitions for silicon validation of foundation IPs
  • Good understanding of Place-and-Route design and associated tools/flow
  • Experience with industry standard synthesis, physical design and STA tools
  • Familiarity with ASIC integration flows
  • Knowledge of tapeout processes and Verification Flows
  • Hands-on experience with ECO implementation
  • Familiarity with DFT insertion and multi-mode timing constraints
  • Strong scripting skills using Perl/Tcl
  • Strong written/verbal communication skills

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