PLL/Clocking Design Engineer
Description For PLL/Clocking Design Engineer
At Apple, our products are revolutionizing the way people live across the globe. Within our Analog-Mixed/Signal group, your role will be crucial in pushing the boundaries of what our technology can achieve. We are dedicated to crafting high-quality, innovative hard IPs that surpass the ordinary, adjusting to the escalating complexity of SOC/PHY designs and multiplying projects within tight production schedules.
In this role, you will leverage your expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple's leadership in innovation and market presence, setting new standards in the tech industry.
Key responsibilities and qualifications include:
- Developing PLL/FLL and frequency synthesis architecture and circuit design
- Expertise in digital and analog approaches, DCO/VCO design (both RO and LC), Fractional-N, SSC, Spur and Jitter cancellation techniques
- Deep understanding of clocking fundamentals, phase noise, jitter analysis, budgeting, and feedback loop dynamics
- Skill in developing System Verilog models and performing behavioral simulations
- Attention to detail and systemic problem-solving
- Innovation and self-directed learning
- Strong teamwork and collaboration skills
This role offers a competitive base pay range between $166,600 and $296,300, along with additional benefits such as stock options, comprehensive medical and dental coverage, retirement benefits, and educational reimbursement opportunities.
Join Apple's culture of innovation, take ownership of your career, and make a substantial impact on society through your work.
Responsibilities For PLL/Clocking Design Engineer
- Develop cutting-edge frequency synthesizers for various applications (Compute, SoC, SerDes, Cellular technologies)
- Design and implement PLL/FLL and frequency synthesis architectures
- Work on digital and analog approaches, DCO/VCO design (RO and LC)
- Implement Fractional-N, SSC, Spur and Jitter cancellation techniques
- Perform clocking fundamentals, phase noise, and jitter analysis
- Develop System Verilog models and conduct behavioral simulations
- Contribute to maintaining Apple's leadership in innovation and market presence
- Collaborate with cross-functional teams to deliver high-quality, innovative hard IPs
Requirements For PLL/Clocking Design Engineer
- BSEE with at least 10 years of relevant experience
- Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design
- Good knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques
- Deep understanding of clocking fundamentals, phase noise, jitter analysis, budgeting, and feedback loop dynamics
- Skilled in developing System Verilog models and performing behavioral simulations
- Exceptional focus on understanding problems and their systemic impacts
- History of innovation and self-directed learning
- Outstanding teamwork capabilities
- Strong productivity and scripting skills
Benefits For PLL/Clocking Design Engineer
- Competitive base pay range
- Opportunity to become an Apple shareholder through stock programs
- Comprehensive medical and dental coverage
- Retirement benefits
- Discounted products and free services
- Educational reimbursement for career advancement
- Potential eligibility for discretionary bonuses or commission payments
- Possible relocation assistance
