PLL/Clocking Design Engineer
Description For PLL/Clocking Design Engineer
At Apple, we're seeking a PLL/Clocking Design Engineer to join our Analog-Mixed/Signal group. In this role, you'll develop cutting-edge frequency synthesizers for various applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple's leadership in innovation and market presence.
Key responsibilities and qualifications include:
- Leveraging expertise in PLL/FLL and frequency synthesis architecture and circuit design
- Demonstrating proficiency in digital and analog approaches, DCO/VCO design (both RO and LC), Fractional-N, SSC, Spur and Jitter cancellation techniques
- Deep understanding of clocking fundamentals, phase noise, jitter analysis, budgeting, and feedback loop dynamics
- Developing System Verilog models and performing behavioral simulations
- Attention to detail and thorough problem-solving skills
- Innovation, self-directed learning, and leadership skills
- Strong teamwork and collaboration abilities
You'll be part of a dynamic environment that thrives on challenges and is fueled by exceptional individuals passionate about continual learning and making a substantial impact. If you excel in dynamic settings, relish collaborative problem-solving, and seek to make a societal impact through your work, this role at Apple could be the perfect fit for you.
Join a culture that encourages you to take ownership of your career, supported by colleagues committed to making a difference in the tech industry.
Responsibilities For PLL/Clocking Design Engineer
- Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies
- Contribute to maintaining Apple's leadership in innovation and market presence
- Apply expertise in digital and analog approaches, DCO/VCO design, Fractional-N, SSC, Spur and Jitter cancellation techniques
- Perform behavioral simulations to explore new architectural performance and impact on loop dynamics
- Collaborate with team members on complex problem-solving
- Drive innovation in PLL/Clocking design
Requirements For PLL/Clocking Design Engineer
- BSEE with at least 10 years of relevant experience
- Proficiency in PLL/FLL and frequency synthesis architecture and circuit design
- Knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques
- Deep understanding of clocking fundamentals, phase noise, jitter analysis, budgeting, and feedback loop dynamics
- Skill in developing System Verilog models and performing behavioral simulations
- Ability to design/debug RTL (a plus)
- Exceptional focus on understanding problems and their systemic impacts
- History of innovation and self-directed learning
- Outstanding teamwork capabilities
- Strong productivity and scripting skills
- Experience with industry-standard design tools (preferred)
