Broadcom is seeking a Senior Memory Design Engineer to contribute to and lead the design and development of Single/Multiport SRAM and Register file compilers in advanced technologies (28nm/16FF/7FF/5FF). The role involves circuit design and simulation of key components, development of critical path and characterization flow, statistical analysis, design tuning, and margin analysis. The ideal candidate will have expertise in high-speed/low-power CMOS circuit design, experience with memory compiler specifications, and proficiency in various design and simulation tools.
Key Responsibilities:
- Lead design and development of SRAM and Register file compilers
- Perform circuit design/simulation of key components
- Develop critical path and characterization flow
- Conduct statistical analysis for compiler target yield sign-off
- Perform design tuning, margin analysis, and sign-off
- Execute logic simulations and timing analysis
- Conduct signal-integrity and power-integrity analysis
Required Skills:
- Expertise in high-speed/low-power CMOS circuit design
- Experience in designing and driving memory compiler specifications
- Deep understanding of split rail and power gating architecture
- Hands-on experience in silicon debug and failure analysis
- Proficiency in Cadence/Mentor schematic/layout editor tools
- Experience with circuit simulation tools (HSPICE, HSIM, XA, FinSim, etc.)
- Understanding of layout design issues in sub-nanometer regime
- Masters Degree with 4+ years or Bachelors Degree with 5+ years of experience
Broadcom offers a challenging and rewarding work environment for talented engineers looking to push the boundaries of memory design. Join our team and contribute to cutting-edge semiconductor solutions that power the world's technology infrastructure.