Senior SRAM Design Engineer

Broadcom is seeking a Senior SRAM Design Engineer to contribute to the design and development of Single/Multiport SRAM and Register file compilers in advanced technologies. The role involves circuit design and simulation of key components, development of critical path and characterization flow, statistical analysis, design tuning, and coordination among various teams.

Key Responsibilities:

1. Lead design and development of SRAM compilers in 16FF/7FF/5FF/3FF Technologies
2. Circuit design/simulation of components like bitcell, WL decoder, Sense Amplifier, Column decoder, and control logic
3. Develop critical path and characterization flow for detailed margin and simulations
4. Perform statistical analysis for Compiler Target yield Sign-Off
5. Design tuning, margin analysis, and sign-off for complete Compiler
6. Conduct logic simulations and timing analysis of key paths in high-speed memory design
7. Coordinate with design, modeling, layout, and verification teams

Required Skills:

1. Expertise in high speed/low power CMOS circuit design, clocking schemes, static and dynamic logic circuits
2. Experience in designing and driving Memory Compilers Specifications to final release
3. Hands-on experience with Cadence/Mentor schematic/layout editor tools
4. Proficiency in circuit simulation, MC analysis, and waveform viewer tools (HSPICE, HSIM, XA, FinSim, XARA, nWave, WV)
5. Experience in Skill/Perl/Python Scripting is a strong plus
6. Understanding of layout design issues and process limitations in FINFET is beneficial

Broadcom offers an exciting opportunity to work on cutting-edge technology in a collaborative environment. Join our team and contribute to the development of next-generation memory solutions.