ASIC RTL Design Engineer, ML Accelerators
Description For ASIC RTL Design Engineer, ML Accelerators
Google is seeking an ASIC RTL Design Engineer to join their Machine Learning Accelerators team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products and data center ML acceleration. As part of the Technical Infrastructure team, you'll work on cutting-edge ASIC development for machine learning computation, contributing to microarchitecture, design, documentation, and implementation of next-generation ML accelerators.
The position offers an exciting opportunity to work with diverse teams pushing the boundaries of hardware innovation. You'll be responsible for creating and reviewing ASIC/SoC subsystem designs, developing SystemVerilog RTL, and collaborating with Design Validation and Physical Design teams. The role requires strong expertise in digital design and SystemVerilog RTL, with preferred experience in ASIC products from concept to silicon.
Working at Google, you'll be part of the team that builds and maintains the architecture behind everything users see online. The Technical Infrastructure team takes pride in being the engineers' engineers, focusing on keeping networks running optimally and ensuring the best user experience possible. This role offers competitive compensation, including base salary, bonus, equity, and comprehensive benefits.
The ideal candidate will have at least 2 years of experience in digital design using SystemVerilog RTL, with preferred qualifications including advanced degrees in relevant fields and experience with SoC IP interfaces and methodologies. You'll be working in either Madison, WI, or Sunnyvale, CA, contributing to Google's mission of developing custom silicon solutions that power the future of their products.
This is an excellent opportunity for someone passionate about hardware design and machine learning acceleration to join a company known for innovation and technical excellence. You'll be part of a team that directly impacts the performance and efficiency of Google's ML infrastructure, working on projects that affect millions of users worldwide.
Responsibilities For ASIC RTL Design Engineer, ML Accelerators
- Work independently and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications
- Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines
- Work with Design Validation (DV) teams to create test plans for, verify, and debug design RTL
- Work with Physical Design teams to ensure design meets physical requirements and timing closure
Requirements For ASIC RTL Design Engineer, ML Accelerators
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
- 2 years of experience in digital design using SystemVerilog RTL
- Experience in digital/ASIC design using SystemVerilog or RTL (preferred)
- Experience in one or more successful ASIC products from concept to silicon (preferred)
- Experience interacting with software, system hardware, and other cross-functional teams (preferred)
- Experience defining SoC IP interfaces and methodologies (preferred)
- Understanding of computer architecture/memory subsystem architecture (preferred)
- Master's degree or PhD in Electrical Engineering, Computer Science, or a related field (preferred)
Benefits For ASIC RTL Design Engineer, ML Accelerators
- Base salary
- Bonus
- Equity
- Benefits package
