ASIC RTL Design Engineer, Silicon

Join Google's platform IP team as an ASIC RTL Design Engineer, where you'll be part of a team that pushes boundaries in developing custom silicon solutions for Google's direct-to-consumer products. You'll work on designing foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs, collaborating with various teams including architecture, software, verification, power, and timing.

The role combines hardware engineering expertise with Google's mission to organize the world's information. You'll be contributing to innovative hardware experiences that impact millions of users worldwide. The position requires strong technical skills in RTL design, microarchitecture development, and hardware validation.

As a member of the team, you'll be responsible for defining detailed microarchitecture specifications, developing RTL using SystemVerilog, performing various quality checks, and participating in the complete silicon development cycle. The role offers an opportunity to work with cutting-edge technology while solving complex technical challenges in silicon design.

The ideal candidate should have experience with RTL design, ARM-based SoCs, and ASIC methodology. Additional expertise in low power estimation, timing closure, and synthesis would be valuable. This position offers the chance to work on next-generation hardware experiences while delivering unparalleled performance, efficiency, and integration in Google's hardware products.