Design Verification Engineer, CPU, Google Cloud
Description For Design Verification Engineer, CPU, Google Cloud
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a CPU Design Verification Engineer, where you'll be part of a team developing custom silicon solutions that power Google's direct-to-consumer products. You'll work on verification of digital designs for server chips, building efficient constrained-random verification environments and managing the full lifecycle of verification processes. The role involves close collaboration with design and verification engineers, requiring expertise in SystemVerilog, UVM, or Specman for comprehensive testing and bug detection. You'll be contributing to Google's hardware infrastructure that supports all Google services and Cloud operations, with a focus on security, efficiency, and reliability. The position offers the opportunity to work on cutting-edge technology that impacts billions of users worldwide, including Google Cloud's Vertex AI platform and various hyperscale computing initiatives. The role requires strong technical skills in digital logic verification, experience with standard IP components, and the ability to work effectively in a collaborative environment. You'll be part of Google's mission to shape the future of hardware experiences, delivering unparalleled performance and efficiency in custom silicon solutions.
Responsibilities For Design Verification Engineer, CPU, Google Cloud
- Plan the verification of digital design blocks
- Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Lead coverage measures to identify verification holes and show progress towards tape-out
Requirements For Design Verification Engineer, CPU, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 3 years of experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs
- Experience verifying digital systems using standard IP components/interconnects
- Experience creating and using verification components and environments in standard verification methodology
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