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RTL Design Engineer, Camera and Machine Learning, Silicon

Google organizes the world's information and makes it universally accessible and useful.
$150,000 - $223,000
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
5+ years of experience
AI · Consumer
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Description For RTL Design Engineer, Camera and Machine Learning, Silicon

Google is seeking an RTL Design Engineer specializing in Camera and Machine Learning for their Silicon team. This role involves developing custom silicon solutions for Google's direct-to-consumer products, focusing on RTL design development for camera and Machine Learning (ML) designs.

Key responsibilities include:

  • Performing Verilog/SystemVerilog RTL coding and debugging
  • Conducting RTL verification using industry-standard methodologies
  • Developing RTL implementations meeting power, performance, and area goals
  • Participating in synthesis, timing/power closure, and FPGA/silicon bring-up
  • Creating tools/scripts to automate tasks and track progress

The ideal candidate should have:

  • A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (Master's or PhD preferred)
  • 5+ years of experience with digital logic design principles and RTL design concepts
  • Proficiency in Verilog or SystemVerilog
  • Experience with logic synthesis techniques and low-power design
  • Familiarity with scripting languages like Perl or Python
  • Knowledge of Camera Image Signal Processor (ISP), Machine Learning IPs, or multimedia IPs
  • Experience with ASIC design methodologies
  • Strong C/C++ programming and software design skills

This role offers the opportunity to shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration for products used by millions worldwide. The position includes a competitive salary range, bonus, equity, and benefits.

Last updated 8 months ago

Responsibilities For RTL Design Engineer, Camera and Machine Learning, Silicon

  • Perform Verilog/SystemVerilog Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks
  • Perform RTL verification using industry standard methodologies. Participate in test planning and coverage analysis
  • Develop RTL implementations that meet engaged power, performance and area goals
  • Participate in synthesis, timing/power closure and Field-programmable Gate Array (FPGA)/silicon bring-up
  • Create tools/scripts to automate tasks and track progress

Requirements For RTL Design Engineer, Camera and Machine Learning, Silicon

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
  • 5 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
  • Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
  • Experience with a scripting language such as Perl or Python

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