RTL Design Engineer

As an RTL Design Engineer for Google Cloud, you will be part of a team creating SoC VLSI design cycles from start to finish. Your responsibilities include:

• Collaborating with design and verification engineers on projects
• Creating architecture definitions with RTL coding
• Running block level simulations
• Contributing to all phases of complex ASIC designs from specification to production
• Working with various teams (architecture, software, verification, power, timing, synthesis) to deliver high-quality SoC/RTL
• Solving technical problems with innovative micro-architecture and practical logic solutions
• Evaluating design options considering complexity, performance, power, and area

You'll be part of the Technical Infrastructure team, which builds and maintains the architecture behind Google's product portfolio. This team is responsible for developing and maintaining data centers, building next-generation Google platforms, and ensuring networks run smoothly for the best user experience.

Key responsibilities include:

• Defining block level design documents (interface protocols, block diagrams, transaction flows, pipelines)
• Performing RTL development (coding and debugging in Verilog, SystemVerilog, VHDL)
• Conducting function/performance simulation debugging and various checks (Lint/CDC/FV/UPF)
• Participating in synthesis, timing/power closure, and FPGA/silicon bring-up
• Contributing to test plans and coverage analysis for block and SOC-level verification
• Communicating and collaborating with multi-disciplined and multi-site teams

Join Google's team of engineers' engineers and contribute to the backbone of Google's technological infrastructure.