RTL Design Engineer

Google is a global technology company that builds innovative products and services used by billions of users worldwide.
Backend
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
AI · Enterprise SaaS · Cloud

Description For RTL Design Engineer

As an RTL Design Engineer for Google Cloud, you will be part of a team creating SoC VLSI design cycles from start to finish. Your responsibilities include:

  • Collaborating with design and verification engineers on projects
  • Creating architecture definitions with RTL coding
  • Running block level simulations
  • Contributing to all phases of complex ASIC designs from specification to production
  • Working with various teams (architecture, software, verification, power, timing, synthesis) to deliver high-quality SoC/RTL
  • Solving technical problems with innovative micro-architecture and practical logic solutions
  • Evaluating design options considering complexity, performance, power, and area

You'll be part of the Technical Infrastructure team, which builds and maintains the architecture behind Google's product portfolio. This team is responsible for developing and maintaining data centers, building next-generation Google platforms, and ensuring networks run smoothly for the best user experience.

Key responsibilities include:

  • Defining block level design documents (interface protocols, block diagrams, transaction flows, pipelines)
  • Performing RTL development (coding and debugging in Verilog, SystemVerilog, VHDL)
  • Conducting function/performance simulation debugging and various checks (Lint/CDC/FV/UPF)
  • Participating in synthesis, timing/power closure, and FPGA/silicon bring-up
  • Contributing to test plans and coverage analysis for block and SOC-level verification
  • Communicating and collaborating with multi-disciplined and multi-site teams

Join Google's team of engineers' engineers and contribute to the backbone of Google's technological infrastructure.

Last updated 14 days ago

Responsibilities For RTL Design Engineer

  • Define block level design documents (interface protocols, block diagrams, transaction flows, pipelines)
  • Perform RTL development (coding and debugging in Verilog, SystemVerilog, VHDL)
  • Conduct function/performance simulation debugging and various checks (Lint/CDC/FV/UPF)
  • Participate in synthesis, timing/power closure, and FPGA/silicon bring-up
  • Contribute to test plans and coverage analysis for block and SOC-level verification
  • Communicate and collaborate with multi-disciplined and multi-site teams

Requirements For RTL Design Engineer

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
  • 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
  • Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques

Interested in this job?

Jobs Related To Google RTL Design Engineer

Software Engineer, Full Life-Cycle Production Systems

Google seeks a Mid-Level Software Engineer for Full Life-Cycle Production Systems in Sunnyvale, CA, offering $136K-$200K salary plus benefits.

Software Engineer III, Infrastructure, Google Cloud

Google Cloud seeks a Software Engineer III for infrastructure development, focusing on large-scale systems and cutting-edge technologies.

Technical Program Manager, Data Center, Compliance (Bahasa)

Google seeks a Technical Program Manager for Data Center Compliance with Bahasa fluency to manage audits and drive compliance programs in Singapore.

Software Engineer, Google Kubernetes Engine and Networking

Google is hiring a Mid-Level Software Engineer for their Kubernetes Engine and Networking team in Warsaw, Poland.

Software Engineer III, Search

Join Google as a Software Engineer III in Search, developing next-gen technologies for billions of users worldwide.