Senior RTL Design Engineer, Silicon
Description For Senior RTL Design Engineer, Silicon
Google is seeking a Senior RTL Design Engineer to join their Silicon team. This role involves developing custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation behind products used by millions worldwide. The ideal candidate will have extensive experience in digital logic design, RTL concepts, and languages like Verilog or SystemVerilog. Key responsibilities include managing micro-architecture definition, integrating IP, performing RTL coding and simulations, and participating in various stages of the ASIC design process. The position offers a competitive salary range of $177,000-$266,000, plus bonus, equity, and benefits. This is an excellent opportunity for experienced engineers to shape the next generation of hardware experiences at one of the world's leading technology companies.
Responsibilities For Senior RTL Design Engineer, Silicon
- Manage micro-architecture definition for a subsystem/ASIC
- Perform integration of internal or external IP
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and FPGA/silicon bring-up
- Participate in test plan and coverage analysis of the sub-system and chip-level verification
Requirements For Senior RTL Design Engineer, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- 6 years of experience with IP Development or Integration
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience with a scripting language like Perl or Python
Benefits For Senior RTL Design Engineer, Silicon
- Equity
- Medical Insurance
