Senior SOC and IP Design Engineer, Google Cloud
Description For Senior SOC and IP Design Engineer, Google Cloud
Join Google Cloud's ML, Systems, & Cloud AI (MSCA) organization as a Senior SOC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's future direct-to-consumer products. This role combines hardware expertise with cutting-edge technology, focusing on designing and implementing critical infrastructure for Google services and Cloud operations.
As part of the team, you'll work on sophisticated SOC and IP design, utilizing your expertise in RTL development, logic synthesis, and hardware verification. You'll be responsible for defining system architecture, developing complex digital logic designs, and ensuring optimal performance through various stages of the development process.
The position offers the opportunity to work with state-of-the-art technology in a collaborative environment, contributing to projects that impact billions of users worldwide. You'll be involved in the complete design cycle, from architectural definition to silicon bring-up, working alongside talented engineers across multiple disciplines.
Google Cloud's commitment to security, efficiency, and reliability will be central to your work, as you help shape the future of hyperscale computing. This role is perfect for someone who combines deep technical knowledge in hardware design with a passion for innovation and the ability to work effectively in a global team setting.
The position offers the chance to work on transformative projects in either Tel Aviv or Haifa, Israel, contributing to Google's mission of advancing technology while maintaining the highest standards of engineering excellence.
Responsibilities For Senior SOC and IP Design Engineer, Google Cloud
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SOC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
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