Senior SoC Design Verification Engineer, Google Cloud
Description For Senior SoC Design Verification Engineer, Google Cloud
Google Cloud is seeking a Senior SoC Design Verification Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of the R&D team, you'll be responsible for building verification components, implementing constrained-random testing, and driving verification closure for server chip designs.
The position requires extensive experience in digital design verification, working with SystemVerilog, UVM, and formal verification tools. You'll collaborate closely with design engineers to ensure functionality and quality of complex SoC designs. The role involves managing the full verification lifecycle, from planning to coverage closure.
This is an opportunity to work on cutting-edge hardware that impacts millions of users worldwide. You'll be part of Google's Technical Infrastructure team, which builds and maintains the architecture behind Google's entire product portfolio. The team takes pride in their engineering excellence and innovative approach to solving complex technical challenges.
The ideal candidate will have strong expertise in ASIC verification, experience with performance verification, and familiarity with memory system architecture. You'll work in either Tel Aviv or Haifa, Israel, contributing to Google's next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration.
Google offers a collaborative environment where you'll work with world-class engineers and have the opportunity to shape the future of hardware technology. The role combines technical depth with strategic thinking, requiring both hands-on verification work and coordination with cross-functional teams.
Responsibilities For Senior SoC Design Verification Engineer, Google Cloud
- Plan the verification of digital design blocks by fully understanding the design specification
- Create and enhance constrained-random verification environments using SystemVerilog and UVM
- Identify and write all types of coverage measures for corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Close coverage measures to identify verification holes and show progress towards tape-out
Requirements For Senior SoC Design Verification Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 8 years of experience with creating and using verification components and environments in standard verification methodology
- Experience verifying digital systems using standard IP components/interconnects
- Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs
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