SoC and IP Design Engineer, Google Cloud
Description For SoC and IP Design Engineer, Google Cloud
Join Google Cloud's innovative hardware team as a SoC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's next-generation cloud infrastructure. As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll work on designing and implementing hardware solutions that support Google's vast array of services including Search, YouTube, and Google Cloud.
The role combines deep technical expertise in digital logic design, RTL development, and system architecture with the opportunity to shape the future of hyperscale computing. You'll be working with cutting-edge technologies, including TPUs and advanced AI platforms like Vertex AI, while focusing on creating efficient, secure, and reliable hardware solutions.
This position offers the chance to work with world-class engineers in a collaborative environment, contributing to projects that directly impact billions of users worldwide. You'll be involved in the complete development cycle, from initial design specifications to silicon bring-up, while working with multi-disciplined teams across different locations.
The ideal candidate will bring strong experience in RTL design, verification, and optimization, combined with knowledge of modern SoC architectures and interfaces. This role provides excellent growth opportunities within Google's hardware organization while working on some of the most challenging and impactful projects in the industry.
Working at Google Cloud means being part of a team that prioritizes innovation, security, and efficiency, while having access to Google's vast resources and technical infrastructure. The position offers the opportunity to work on projects that are pushing the boundaries of what's possible in cloud computing and artificial intelligence hardware acceleration.
Responsibilities For SoC and IP Design Engineer, Google Cloud
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug
- Participate in synthesis, timing/power closure, and Application-specific integrated circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 3 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
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