SoC UPF Design Engineer
Description For SoC UPF Design Engineer
Google Cloud is seeking a SoC UPF Design Engineer to join their Technical Infrastructure team, focusing on developing custom silicon solutions for data center accelerators. This role combines hardware expertise with software development, requiring deep knowledge of RTL design and power management through UPF specifications.
The position offers an opportunity to work on cutting-edge technology that powers Google's direct-to-consumer products and cloud infrastructure. You'll be part of a diverse team that pushes boundaries in hardware innovation, working on SoC-level RTL design for data center accelerators. The role involves owning top-level RTL, architecture, design and implementation of global communication busses, and integration of complex ASIC designs.
As a cross-functional position, you'll interact with numerous ASIC development teams and own deliverables for Physical Design, Verification, Validation, and Firmware teams. The role requires expertise in low-power design techniques, SOC implementation standards, and formal verification methods. You'll contribute to creating methodologies that enable efficient design environments for all ASIC engineers.
The Technical Infrastructure team is proud to be the engineers' engineers, maintaining data centers and building next-generation Google platforms. The role offers competitive compensation, including a base salary range of $127,000-$187,000, plus bonus, equity, and comprehensive benefits. This is an excellent opportunity for someone passionate about hardware design and looking to make a significant impact on Google's infrastructure.
Responsibilities For SoC UPF Design Engineer
- Contribute to the development and successful delivery of complex silicon systems
- Design and implement RTL code for various digital blocks, including complex control logic, and on-chip data paths
- Develop and maintain Unified Power Format (UPF) specifications for power management
- Take ownership of power signoff using industry standard tools coordinating deliverables from block owners
- Collaborate with verification and physical design engineers to ensure functionality and power integrity
- Contribute to the development and improvement of design flows, tools and methodologies
Requirements For SoC UPF Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
- 3 years of experience with RTL coding using Verilog/SystemVerilog
- 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips
Benefits For SoC UPF Design Engineer
- bonus
- equity
- benefits
