ASIC Engineer, Design

Meta is seeking an ASIC Design Engineer to join their Infrastructure organization, focusing on developing cutting-edge ASICs for machine learning, video transcoding, and network acceleration applications. This role combines hardware engineering expertise with Meta's mission to build technologies that connect people and communities.

The position offers an opportunity to work on complex and impactful projects in Meta's AI Infrastructure team. As an ASIC Design Engineer, you'll be responsible for architecture exploration, micro-architecture development, and working with IP integration. You'll collaborate closely with verification, emulation, and implementation teams to ensure successful design outcomes.

The ideal candidate should have at least 2 years of experience in micro-architecture and RTL development, with strong skills in Verilog and System Verilog. A background in Computer Science or Computer Engineering is required, with preferred experience in CPU, NOC, Memory, and Peripheral Subsystems.

This role offers competitive compensation ranging from $114,000 to $166,000 per year, plus bonus, equity, and comprehensive benefits. Working at Meta provides the opportunity to impact billions of users while working with cutting-edge technology in AI and hardware development.

Meta's commitment to innovation in AI infrastructure makes this an exciting opportunity for hardware engineers looking to work on next-generation ASIC development. The company's scale and resources provide an excellent platform for professional growth and technical advancement in the field of hardware design.

The position is available in either Sunnyvale, CA or Austin, TX, offering the chance to work in major tech hubs with strong engineering communities. Meta's inclusive culture and commitment to equal employment opportunity ensure a supportive and diverse work environment.