Design Verification Engineer 2
Description For Design Verification Engineer 2
Microsoft's Silicon team is seeking a Design Verification Engineer to join their Artificial Intelligence System on Chip (AISoC) team. This role is crucial in delivering premium-quality designs for cutting-edge silicon solutions. The position involves working on diverse systems from Xbox gaming to Azure cloud servers and augmented reality platforms. The ideal candidate will have strong experience in design verification, computer architecture, and RTL debugging.
The role offers an exciting opportunity to work on innovative technology that impacts millions of users worldwide. As part of Microsoft's mission to empower every person and organization, you'll be contributing to groundbreaking AI silicon development. The position combines technical depth in hardware engineering with the breadth of Microsoft's technology stack.
The work environment promotes a growth mindset and collaboration, with up to 50% work-from-home flexibility. You'll be part of a team delivering custom IP and SoC designs that push the boundaries of performance and efficiency. The role offers comprehensive benefits, including industry-leading healthcare, educational resources, and work-life balance support.
This is an ideal opportunity for an experienced verification engineer who wants to impact the future of AI hardware while working with cutting-edge technology at a global scale. The position offers both technical challenges and career growth opportunities in one of the world's leading technology companies.
Responsibilities For Design Verification Engineer 2
- Plan verification of complex design IP/SoC interacting with architecture and design engineers
- Create and enhance constrained-random verification environments using SystemVerilog and UVM
- Develop tests using UVM or C/C++
- Analyse and debug test failures with designers
- Identify and write functional coverage for stimulus and corner cases
- Close coverage to plug verification holes and meet tape out requirements
Requirements For Design Verification Engineer 2
- 3+ years of experience in design verification with proven track record of delivering complex CPU or SoC IP's
- Knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments
- Good understanding of computer architecture
- Substantial background in debugging RTL (Verilog) designs and simulation/emulation environments
- Scripting language such as Python or Perl
Benefits For Design Verification Engineer 2
- Industry leading healthcare
- Educational resources
- Discounts on products and services
- Savings and investments
- Maternity and paternity leave
- Generous time away
- Giving programs
- Opportunities to network and connect
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