DFT Engineer

NVIDIA is seeking a DFT Engineer to join their team working on groundbreaking innovations in Design-for-Test Engineering. The role involves crafting creative solutions for DFT architecture, verification, and post-silicon validation on some of the industry's most complex semiconductor chips.

As a DFT Engineer, you will be responsible for:

• Designing and implementing state-of-the-art test access mechanisms, IO BIST, memory BIST, and scan compression
• Verifying and performing silicon bringup of Scan ATPG and other DFT features
• Developing and deploying DFT methodologies for next-generation products
• Innovating to improve the quality of DFT methods
• Collaborating with multi-functional teams to incorporate DFT features into chips

The ideal candidate should have:

• BSEE or MSEE from reputed institutions with 1+ years of experience
• Strong knowledge of static timing analysis, ECO, ASIC/Logic Design Flow, HDL, and Digital logic design
• Experience in RTL and Gates verification and simulation
• Familiarity with BIST architecture and JTAG/IEEE1149.1/IEEE1500
• Strong DFT knowledge in Scan ATPG, compression techniques, and memory test
• Excellent analytical and problem-solving skills
• Strong coding skills in industry-standard scripting languages
• Exceptional written and oral communication skills

This role offers the opportunity to work on cutting-edge technology at a company that has continuously reinvented itself over two decades. NVIDIA's innovations have sparked the growth of the PC gaming market, redefined modern computer graphics, revolutionized parallel computing, and ignited the era of AI and deep learning.

Join NVIDIA to be part of a "learning machine" that constantly evolves by adapting to new opportunities that are challenging, unique, and impactful to the world. This is your chance to contribute to amplifying human imagination and intelligence through technology.

Note: The role may involve occasional travel and some late-hour online meetings during critical milestones.