Floorplan CAD Engineer

Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of RTL2GDS solutions for the Snapdragon chips powering billions of mobile devices. The position requires Floorplanning experience and CAD development skills to define and develop implementation tools and methodologies for PPA, Quality and shortening design cycle time, in close collaboration with Snapdragon Physical Design and Floorplanning teams. Qualcomm is using leading edge internal and EDA technologies in the Floorplan domain, including pioneering in genAI/ML, and developing good-by-construction automation for the most complex multi-voltage rectilinear macro-dominated designs of the industry.

This role's responsibilities will include:

• Improving the SoC Floorplan methodology for diverse Mobile, Compute, AI, IoT Snapdragon chips.
• Developing Floorplan tools and flows for both automation and enablement of new features for the foundry advanced process nodes, collaborate with AI team on ground-breaking initiatives for die area reduction and turn-around time reduction.
• Project Global CAD Floorplan solutions to the Snapdragon design teams, analyze their requests, and address their requests through ticket queues.
• Interfacing with EDA vendors to enable production-ready tool sets that satisfy project's requirement.
• Setting up, augmenting, and maintaining a regression of complex Floorplan designs
• Innovating on Floorplan techniques and physical cells for die area reduction, leading to participation to patents.

Preferred Qualifications:

• Bachelor's degree or Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field.
• 1-4 years of experience in Floorplanning of SoCs at either top-level or block-level.
• 1-4 years of experience with scripting tools and programming languages: Python and TCL preferred.

Principal Duties and Responsibilities:

• Participate to the Floorplan flow enablement for foundry advanced process nodes.
• Participate to the development of the Floorplan Flow, including the tuning of design recipes to address specific objectives such as area, turn-around time on various subsystems such as Modem, GPU, CPU, DDR, Camera, Video, NSP.
• Interface and drive EDA vendor Application Engineers on the resolution of Floorplan problems faced by the Snapdragon design teams.
• Participate to the specification of new Floorplan CAD solutions addressing the PPA requirements of the design teams.
• Deep dive on Floorplan issues, such as tapcells incorrect placement, power grid DRC, incorrect placement of chaining of head switches, long macro snapping runtime, latch-up DRC etc.
• Participate along with Qualcomm talented AI team to R&D initiatives driving differentiation in terms of die area reduction and turn-around time.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

Qualcomm is an equal opportunity employer and offers a competitive annual discretionary bonus program and opportunity for annual RSU grants. The highly competitive benefits package is designed to support your success at work, at home, and at play.